The present invention relates to a semiconductor device in which stress is applied to a channel region, and a method of manufacturing the semiconductor device.
Many reports on techniques for improving driving capability without depending on a scaling law have recently been given. The known techniques enhance driving capability by applying stress to a silicon region (for example a silicon substrate) in which a channel region is formed, and thereby increasing mobility of electrons and holes. As these techniques, a method has been put to practical use in which method a drain-source part is dug down by silicon etching, and a silicon compound having a different lattice constant from that of silicon (Si) is grown by an epitaxial growth method, whereby stress is applied to a channel (see Japanese Patent Laid-Open No. 2000-315789, for example).
In addition, various attempts have been made, including stress liner techniques that distort a channel by forming a covering of a silicon nitride film having stress after formation of the transistor, techniques that distort a channel by using a film having stress as a part of burying materials for STI (Shallow Trench Isolation), and the like.
The mechanism will be described with reference to a schematic diagram. FIGS. 10A and 10B show the three-dimensional directions of stresses most effective when applied to the respective transistors of a pMOSFET shown in FIG. 10A and an nMOSFET shown in FIG. 10B to distort a channel. Effective stress common to the NMOS and the PMOS is applied in a direction of stretching an active region in an x-direction.
A section in a gate width direction (a direction orthogonal to a source-to-drain region direction) of a two-dimensional type (planar) MOS transistor in related art will be described with reference to a schematic configuration sectional view of FIG. 11. It is known that as shown in FIG. 11, an insulating film (high density plasma (HDP) or the like) when buried in a trench 115 formed in a semiconductor substrate 111 to form an element isolation regions 113 of an STI structure has compressive stress. The stress applied to a channel region 114 of the transistor acts in a direction of degrading mobility (the direction of arrows).
On the other hand, as transistor generations have succeed, many researches have been conducted into transistors having a three-dimensional structure in place of the two-dimensional type (planar) transistor in related art. A typical transistor is referred to as a fin gate transistor, in which a gate electrode is disposed on a silicon substrate with a gate dielectric interposed between the gate electrode and the silicon substrate, the gate dielectric covering a channel region part of a fin part formed so as to be projected in the shape of a fin (see Japanese Patent Laid-Open No. 2006-12924, for example). In addition, a tri gate transistor using, as a channel, not only an upper side surface of a semiconductor substrate in which a trench is formed but also a side wall part of an upper side of the trench has been reported (see Japanese Patent Laid-Open No. 2002-198532, for example).
FIG. 12 is a three-dimensional schematic diagram of an ordinary MOS transistor. FIG. 13 is a vertical sectional view including a line A-A′ of FIG. 12. When silicide layers 131 and 132 for lowering resistance are formed on the surfaces of source-drain regions 127 and 128 in a transistor 101 having a structure in which a channel region 114 and the source-drain regions 127 and 128 project from the surface of a semiconductor substrate 111, as shown in FIGS. 12 and 13, a leak occurs as a result of the silicide layers 131 and 132 being close to or in contact with the PN junction of the source-drain regions 127 and 128 formed by ion implantation and projected from the surface of the semiconductor substrate 111.